The ALMA Digitizer (DG) Demultiplexer Abstract
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ALMA Memo # 510
The ALMA Digitizer (DG) Demultiplexer
:
Design, Performances in DG Assembly and Production Acceptance
Tests
Cyril Recoquillon
Alain Baudry
Jean-Baptiste Begueret
Stephane Gauffre
Guy Montignac
2004-12-13
Keywords:Demultiplexer/Deserializer, SiGe technology, High-speed digital circuit, Self-test, Digitizer assembly
Abstract: A high frequency, low power 1:16 deserializer has been developed using the 0.25µm BiCMOS SiGe technology from ST Microelectronics to meet the ALMA project requirements. The input shift register is clocked at 4 GHz and the output data are transferred at 250 MHz. Nominal operation has been observed up to 8 GHz. With 2.5 V supply, the circuit dissipates around 650 mW an especially low value compared to existing similar circuits. The chip is available in an industrial package and exhibits low thermal resistance (about 25 °C/W) thus implying long lifetime as required for the ALMA project. Functional tests including those performed with a self-test block embedded in the deserializer are briefly described. Our deserializer is integrated in a prototype ALMA Digitizer assembly which includes a 3-bit (8-level), 4 GS/s sampler developed with the same SiGe process. Based on Digitizer state counts measurements, Allan variance tests and long term operation in the laboratory environment, we conclude that the prototype Digitizer assembly is operational. The deserializer chip has reached the final production stage after static and dynamic qualification tests have been performed on a first restricted number of production chips.
View a pdf version of ALMA Memo #510.
